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Espressif Systems /ESP32-P4 /CACHE /L2_CACHE_ACCESS_ATTR_CTRL

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Interpret as L2_CACHE_ACCESS_ATTR_CTRL

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (L2_CACHE_ACCESS_FORCE_CC)L2_CACHE_ACCESS_FORCE_CC 0 (L2_CACHE_ACCESS_FORCE_WB)L2_CACHE_ACCESS_FORCE_WB 0 (L2_CACHE_ACCESS_FORCE_WMA)L2_CACHE_ACCESS_FORCE_WMA 0 (L2_CACHE_ACCESS_FORCE_RMA)L2_CACHE_ACCESS_FORCE_RMA

Description

L2 cache access attribute control register

Fields

L2_CACHE_ACCESS_FORCE_CC

Set this bit to force the request to l2 cache with cacheable attribute, otherwise, the attribute is propagated from L1 cache or CPU, it could be one of cacheable and non-cacheable.
L2_CACHE_ACCESS_FORCE_WB

Set this bit to force the request to l2 cache with write-back attribute, otherwise, the attribute is propagated from L1 cache or CPU, it could be one of write-back and write-through.
L2_CACHE_ACCESS_FORCE_WMA

Set this bit to force the request to l2 cache with write-miss-allocate attribute, otherwise, the attribute is propagated from L1 cache or CPU, it could be one of write-miss-allocate and write-miss-no-allocate.
L2_CACHE_ACCESS_FORCE_RMA

Set this bit to force the request to l2 cache with read-miss-allocate attribute, otherwise, the attribute is propagated from L1 cache or CPU, it could be one of read-miss-allocate and read-miss-no-allocate.

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/espressif/svd